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description available in either 8-pin dip or so - 8 package style respec - tively, the hcpl-7723 or hcpl-0723 optocoupler utilize the latest cmos ic technology to achieve out standing speed performance of minimum 50 mbd data rate and 2 ns maximum pulse width distortion. basic building blocks of hcpl-7723/0723 are a cmos led driver ic, a high speed led and a cmos detector ic. a cmos logic input signal controls the led driver ic, which supplies current to the led. the detector ic incorporates an integrated photodiode, a high speed transimpedance amplifer, and a voltage comparator with an output driver. functional diagram 8 7 6 1 3 shield 5 2 4 **v dd1 v i nc* gnd 1 v dd2 ** v o gnd 2 v i , input led1 h l off on truth table (positive logic) nc* i o led1 v o , output h l * pin 3 is the anode of the internal led and must be left unconnected for guaranteed datasheet performance. pin 7 is not connected internally. ** a 0.1 f bypass capacitor must be connected between pins 1 and 4, and 5 and 8. caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation, which may be induced by esd. features ? +5 v cmos compatibility ? high speed: 50 mbd min. ? 2 ns max. pulse width distortion ? 22 ns max. prop. delay ? 16 ns max. prop. delay skew ? 10 kv/s min. common mode rejection ? C40 to 85c temperature range ? safety and regulatory approvals: ul recognized C 5000 v rms for 1 min. per ul1577 for hcpl-7723 for option 020 C 3750 v rms for 1 min. per ul1577 for hcpl-0723 csa component acceptance notice #5 iec/en/din en 60747-5-5 C v iorm = 630 v peak for hcpl-7723 option 060 C v iorm = 567 v peak for hcpl-0723 option 060 applications ? digital feldbus isolation: cc-link, devicenet, profbus, sds, isolated a/d or d/a conversion ? multiplexed data transmission ? high speed digital input/output ? computer peripheral interface ? microprocessor system interface hcpl-7723/0723 50 mbd 2 ns pwd high speed cmos optocoupler data sheet lead (pb) free rohs 6 fully compliant rohs 6 fully compliant options available; -xxxe denotes a lead-free product
2 package outline drawings hcpl-7723 8-pin dip package 9.65 0.25 (0.380 0.010) 1.78 (0.070) max. 1.19 (0.047) max. a xxxxv yyww date code 1.080 0.320 (0.043 0.013) 2.54 0.25 (0.100 0.010) 0.51 (0.020) min. 0.65 (0.025) max. 4.70 (0.185) max. 2.92 (0.115) min. dimensions in millimeters and (inches). 5 6 7 8 4 3 2 1 5 typ. 0.254 + 0.076 - 0.051 (0.010 + 0.003) - 0.002) 7.62 0.25 (0.300 0.010) 6.35 0.25 (0.250 0.010) type number *option 300 and 500 not marked. note: floating lead protrusion is 0.15 mm (6 mils) max. option 060 code* 3.56 0.13 (0.140 0.005)
3 hcpl-7723 package with gull wing surface mount option 300 hcpl-0723 small outline so-8 package 0.635 0.25 (0.025 0.010) 12 nom. 9.65 0.25 (0.380 0.010) 0.635 0.130 (0.025 0.005) 7.62 0.25 (0.300 0.010) 5 6 7 8 4 3 2 1 9.65 0.25 (0.380 0.010) 6.350 0.25 (0.250 0.010) 1.016 (0.040) 1.27 (0.050) 10.9 (0.430) 2.0 (0.080) land pattern recommendation 1.080 0.320 (0.043 0.013) 3.56 0.13 (0.140 0.005) 1.780 (0.070) max. 1.19 (0.047) max. 2.54 (0.100) bsc dimensions in millimeters (inches). lead coplanarity = 0.10 mm (0.004 inches). note: floating lead protrusion is 0.15 mm (6 mils) max. 0.254 + 0.076 - 0.051 (0.010 + 0.003) - 0.002) xxxv yww 8 7 6 5 4 3 2 1 5.994 0.203 (0.236 0.008) 3.937 0.127 (0.155 0.005) 0.406 0.076 (0.016 0.003) 1.270 (0.050) bsc 5.080 0.127 (0.200 0.005) 3.175 0.127 (0.125 0.005) 1.524 (0.060) 45 x 0.432 (0.017) 0.228 0.025 (0.009 0.001) type number (last 3 digits) date code 0.305 (0.012) min. total package length (inclusive of mold flash) 5.207 0.254 (0.205 0.010) dimensions in millimeters (inches). lead coplanarity = 0.10 mm (0.004 inches) max. option number 500 not marked. note: floating lead protrusion is 0.15 mm (6 mils) max. 0.203 0.102 (0.008 0.004) 7 pin one 0 ~ 7 * * 7.49 (0.295) 1.9 (0.075) 0.64 (0.025) land pattern recommendation
4 device selection guide 8-pin dip (300 mil) small outline so-8 hcpl-7723 hcpl-0723 ordering information hcpl-0723 and hcpl-7723 are ul recognized with 3750 vrms for 1 minute per ul1577. option part rohs non rohs surface gull tape ul 5000 vrms/ iec/en/din number compliant compliant package mount wing & reel 1 minute rating en 60747-5-5 quantity -000e no option 300 mil dip-8 50 per tube -300e -300 x x 50 per tube -500e -500 x x x 1000 per reel -020e -020 x 50 per tube hcpl-7723 -320e -320 x x x 50 per tube -520e -520 x x x x 1000 per reel -060e -060 x 50 per tube -360e -360 x x x 50 per tube -560e -560 x x x x 1000 per reel -000e no option so-8 x 100 per tube hcpl-0723 -500e -500 x x 1500 per reel -060e -060 x x 100 per tube -560e -560 x x x 1500 per reel to order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. example 1: hcpl-7723-560e to order product of gull wing surface mount package in tape and reel packaging with iec/en/din en 60747-5-5 safety approval and rohs compliant. example 2: hcpl-0723 to order product of small outline so-8 package in tube packaging and non rohs compliant. option datasheets are available. contact your avago sales representative or authorized distributor for information. remarks: the notation #xxx is used for existing products, while (new) products launched since july 15, 2001 and rohs compliant will use Cxxxe.
5 regulatory information the hcpl-7723/0723 have been approved by the following organizations: ul recognized under ul1577, component recognition program, file e55361. csa approved under csa component acceptance notice #5, file ca88324. iec/en/din en 60747-5-5 approved with maximum working insulation voltage: v iorm = 567 v peak for hcpl-0723, v iorm = 630 v peak for hcpl-7723 solder refow profle recommended refow condition as per jedec standard, j-std-020 (latest revision). non-halide flux should be used. insulation and safety related specifcations value parameter symbol 7723 0723 units conditions minimum external air gap l(i01) 7.1 4.9 mm measured from input terminals to output (clearance) terminals, shortest distance through air. minimum external tracking l(i02) 7.4 4.8 mm measured from input terminals to output (creepage) terminals, shortest distance path along body. minimum internal plastic gap 0.08 0.08 mm insulation thickness between emitter and (internal clearance) detector; also known as distance through insulation. tracking resistance cti 175 175 volts din iec 112/vde 0303 part 1 (comparative tracking index) isolation group iiia iiia material group (din vde 0110, 1/89, table 1)
6 all avago data sheets report the creepage and clearance inherent to the optocoupler component itself. these dimensions are needed as a starting point for the equipment designer when determining the circuit insula - tion requirements. however, once mounted on a printed circuit board, minimum creepage and clearance require - ments must be met as specifed for individual equipment standards. for creepage, the shortest distance path along the surface of a printed circuit board between the solder fllets of the input and output leads must be considered. there are recommended techniques such as grooves and ribs, which may be used on a printed circuit board to achieve desired creepage and clearances. creepage and clearance distances will also change depending on factors such as pollution degree and insulation level. iec/en/din en 60747-5-5 insulation characteristics (option 060) description symbol characteristic unit hcpl-7723 hcpl-0723 installation classifcation per din vde 0110, table 1 for rated mains voltage 150 v rms i C iv i C iv for rated mains voltage 300 v rms i C iii i C iii for rated mains voltage 600 v rms i C iv i C iii climatic classifcation 55/85/21 55/85/21 pollution degree (din vde 0110/39) 2 2 maximum working insulation voltage v iorm 630 567 v peak input to output test voltage, method b* v iorm x 1.875 = v pr , 100% production test with t m =1 sec, partial discharge < 5 pc v pr 1181 1063 v peak input to output test voltage, method a* v iorm x 1.6 = v pr , type and sample test, t m =10 sec, partial discharge < 5 pc v pr 1008 907 v peak highest allowable overvoltage (transient overvoltage t ini = 60 sec) v iotm 8000 6000 v peak safety-limiting values C maximum values allowed in the event of a failure case temperature t s 175 150 c input current i s, input 230 150 ma output power p s, output 600 600 mw insulation resistance at t s , v io = 500 v r s 10 9 10 9 ? *refer to the optocoupler section of the isolation and control component designers catalog, under product safety regulations section iec/en/ din en 60747-5-5, for a detailed description of method a and method b partial discharge test profles.
7 absolute maximum ratings parameter symbol min. max. units storage temperature t s C55 125 c ambient operating temperature [1] t a C40 85 c supply voltages v dd1 , v dd2 0 6.0 volts input voltage v i C0.5 v dd1 +0.5 volts output voltage v o C0.5 v dd2 +0.5 volts average output current i o 10 ma lead solder temperature 260c for 10 sec., 1.6 mm below seating plane solder refow temperature profle see solder refow temperature profle section recommended operating conditions parameter symbol min. max. units ambient operating temperature t a C40 85 c supply voltages v dd1 , v dd2 4.5 5.5 v logic high input voltage v ih 2.0 v dd1 v logic low input voltage v il 0.0 0.8 v input signal rise and fall times t r, t f 1.0 ms electrical specifcations test conditions that are not specifed can be anywhere within the recommended operating range. all typical specifcations are at t a = +25c, v dd1 = v dd2 = +5 v. parameter symbol min. typ. max. units test conditions logic low input supply current [2] i dd1l 8.4 10 ma v i = 0 v; figure 1 logic high input supply current [2] i dd1h 0.6 3 ma v i = v dd1 ; figure 2 output supply current i dd2l 2.1 5 ma figure 3 i dd2h 2.0 5 ma figure 4 input current i i C10 10 a logic high output voltage v oh 4.4 5.0 v i o = C20 a, v i = v ih 4.0 4.8 v i o = C4 ma, v i = v ih logic low output voltage v ol 0 0.1 v i o = 20 a, v i = v il 0.5 1.0 v i o = 4 ma, v i = v il
8 switching specifcations test conditions that are not specifed can be anywhere within the recommended operating range. all typical specifcations are at t a = +25c, v dd1 = v dd2 = +5 v. parameter symbol min. typ. max. units test conditions propagation delay time to logic t phl 16 22 ns c l = 15 pf cmos signal levels; figure 5 low output [3] propagation delay time to logic t plh 16 22 ns c l = 15 pf cmos signal levels; figure 5 high output [3] pulse width pw 20 ns c l = 15 pf cmos signal levels maximum data rate 50 mbd c l = 15 pf cmos signal levels pulse width distortion [4] |t phl - t plh | |pwd| 1 2 ns c l = 15 pf cmos signal levels; figure 6 propagation delay skew [5] t psk 16 ns c l = 15 pf cmos signal levels output rise time (10% C 90%) t r 8 ns c l = 15 pf cmos signal levels output fall time (90% - 10%) t f 6 ns c l = 15 pf cmos signal levels common mode transient immunity |cm h | 10 15 kv/s v cm = 1000 v , t a = 25c, at logic high output [6] v i = v dd1, v o > 0.8 v dd2 common mode transient immunity |cm l | 10 15 kv/s v cm = 1000 v , t a = 25c, at logic low output [6] v i = 0 v , v o < 0.8 v
9 package characteristics all typical specifcations are at t a = 25c. parameter symbol min. typ. max. units test conditions input-output momentary C7723 v iso 3750 v rms rh 50%, t = 1 min, withstand voltage [7,8,9] option 020 5000 t a = 25c C0723 3750 input-output resistance [7] r i-o 10 12 ? v i-o = 500 v dc input-output capacitance c i-o 0.6 pf f = 1 mhz input capacitance [10] c i 3.0 pf input ic junction-to-case C7723 jci 145 c/w thermocouple located at thermal resistance C0723 160 center underside of package output ic junction-to-case C7723 jco 145 c/w thermal resistance C0723 135 package power dissipation p pd 150 mw notes: 1. absolute maximum ambient operating temperature means the device will not be damaged if operated under these conditions. it does not guarantee functionality. 2. the led is on when v i is low and off when v i is high. 3. t phl propagation delay is measured from the 50% level on the falling edge of the vi signal to the 50% level of the falling edge of the v o sig - nal. t plh propagation delay is measured from the 50% level on the rising edge of the vi signal to the 50% level of the rising edge of the v o signal. 4. pwd is defned as |t phl - t plh |. %pwd (percent pulse width distortion) is equal to the pwd divided by pulse width. 5. t psk is equal to the magnitude of the worst case diference in t phl and/or t plh that will be seen between units at any given temperature within the recommended operating conditions. 6. cmh is the maximum common mode voltage slew rate that can be sustained while maintaining v o > 0.8 v dd2 . cml is the maximum com - mon mode voltage slew rate that can be sustained while maintaining v o < 0.8 v. the common mode voltage slew rates apply to both rising and falling common mode voltage edges. 7. device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together. 8. in accordance with ul1577, each hcpl-0723 is proof tested by applying an insulation test voltage 4500 vrms for 1 second (leakage detec - tion current limit, i i-o 5 a). each hcpl-7723 is proof tested by applying an insulation test voltage 4500 vrms for 1 second (leakage detec - tion current limit. i i-o 5 a.) 9. the input-output momentary withstand voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. for the continuous voltage rating refer to your equipment level safety specifcation or avago application note 1074 entitled optocoupler input-output endurance voltage. 10. c i is the capacitance measured at pin 2 (v i ).
10 6.5 7.0 7.5 8.0 8.5 9.0 - 40 - 20 0 20 40 60 80 100 i dd1l - logic low input supply t a (c) 0.4 0.45 0.5 0.55 0.6 - 40 - 20 0 20 40 60 80 100 t a (c) i dd1h - logic high input supply 1.0 1.5 2.0 2.5 3.0 - 40 - 20 0 20 40 60 80 100 i dd2l - logic low output supply t a (c) 1 1 . 5 2 2 . 5 3 - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 t a (c) i dd2h - logic high output supply current (ma) current (ma) current (ma) current (ma) 0 0 . 2 0 . 4 0 . 6 0 . 8 1 1 . 2 1 . 4 1 . 6 1 . 8 2 - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 p w d ( n s ) t a (c) t plh t phl -40 -20 0 20 40 60 80 100 10 12 14 16 18 20 22 t phl , t plh (ns) t a (c) figure 1: typical logic low input supply current vs. temperature figure 2. typical logic high input supply current vs. temperature figure 3. typical logic low output supply current vs. temperature figure 4. typical logic high output supply current vs. temperature figure 5. typical propagation delay vs. temperature figure 6. typical pulse width distortion vs. temperature
11 application information bypassing and pc board layout the hcpl-7723/0723 optocouplers are extremely easy to use. no external interface circuitry is required because the hcpl-7723/0723 use high-speed cmos ic technol - ogy allowing cmos logic to be connected directly to the inputs and outputs. as shown in figure 7, the only external components required for proper operation are two bypass capacitors. capacitor values should be between 0.01 f and 0.1 f. for each capacitor, the total lead length between both ends of the capacitor and the power-supply pins should not exceed 20 mm. figure 8 illustrates the recommended printed circuit board layout for the hcpl-7723/0723. figure 9. timing diagram to illustrate propagation delay, tplh and tphl. input t plh t phl output v i v o 10% 90% 90% 10% v oh v ol 0 v 50% 5 v cmos 2.5 v cmos figure 7. functional diagram. figure 8. recommended printed circuit board layout. propagation delay, pulse-width distortion and propa - gation delay skew propagation delay is a fgure of merit which describes how quickly a logic signal propagates through a system as illustrated in figure 9. the propagation delay from low to high (t plh ) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. similarly, the propagation delay from high to low (t phl ) is the amount of time required for the input signal to propagate to the output, causing the output to change from high to low. 7 5 6 8 2 3 4 1 gnd 2 c1 c2 nc v dd2 nc v o v dd1 v i 720 yww c1, c2 = 0.01 f to 0.1 f gnd 1 v dd2 c1 c2 720 yww v o gnd 2 v dd1 v i gnd 1 c1, c2 = 0.01 f to 0.1 f
for product information and a complete list of distributors, please go to our website: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies limited in the united states and other countries. data subject to change. copyright ? 2005-2013 avago technologies limited. all rights reserved. obsoletes av01-0566en av02-0643en - february 26, 2013 pulse-width distortion (pwd) is the diference between t phl and t plh and often determines the maximum data rate capability of a transmission system. pwd can be expressed in percent by dividing the pwd (in ns) by the minimum pulse width (in ns) being transmitted. typically, pwd on the order of 20-30% of the minimum pulse width is tolerable. propagation delay skew, t psk , is an important parameter to consider in parallel data applica tions where synchro - nization of signals on parallel data lines is a concern. if the parallel data is being sent through a group of opto - couplers, diferences in propagation delays will cause the data to arrive at the outputs of the optocouplers at diferent times. if this diference in propagation delay is large enough it will determine the maximum rate at which parallel data can be sent through the optocou - plers. propagation delay skew is defned as the diference between the minimum and maximum propagation delays, either t plh or t phl , for any given group of opto - couplers which are operating under the same conditions (i.e., the same drive current, supply voltage, output load, and operating temperature). as illustrated in figure 10, if the inputs of a group of optocouplers are switched either on or off at the same time, t psk is the diference between the shortest propagation delay, either t plh or t phl , and the longest propagation delay, either t plh or t phl . figure 10. timing diagram to illustrate propagation delay skew, tpsk. 50% 50% t psk v i v o v i v o 2.5 v, cmos 2.5 v, cmos data inputs clock data outputs clock t psk t psk figure 11. parallel data transmission example. as mentioned earlier, t psk can determine the maximum parallel data transmission rate. figure 11 is the timing diagram of a typical parallel data application with both the clock and data lines being sent through the opto - couplers. the fgure shows data and clock signals at the inputs and outputs of the optocouplers. in this case the data is assumed to be clocked of of the rising edge of the clock. propagation delay skew represents the uncertainty of where an edge might be after being sent through an op - tocoupler. figure 11 shows that there will be uncertainty in both the data and clock lines. it is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled, or some of the data outputs may start to change before the clock signal has arrived. from these consid - erations, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice t psk . a cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem. the hcpl-7723/0723 optocouplers ofer the advantage of guaranteed specifcations for propagation delays, pulse- width distortion, and propagation delay skew over the recommended temperature and power supply ranges.

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